Freescale Semiconductor /MK61F15WS /MCG /C12

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Interpret as C12

CME2=0, LOLIE1=0

MCG Control 12 Register

VDIV1	VCO1 Divider
CME2	Clock Monitor Enable2 0 (0): External clock monitor for OSC1 is disabled. 1 (1): Generate a reset request on loss of external clock on OSC1.
RESERVED	Reserved
LOLIE1	PLL1 Loss of Lock Interrupt Enable 0 (0): No interrupt request is generated on loss of lock on PLL1. 1 (1): Generate an interrupt request on loss of lock on PLL1.

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